1. Technical Field
The present disclosure generally relates to information handling systems and in more specifically to flexible interconnections between two endpoints in an information handling system. Still more particularly, the present disclosure relates to the allocation and reallocation of peripheral component interconnect (PCI) lanes of a PCI connector.
2. Description of the Related Art
As the value and use of information continue to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
An information handling system (IHS) typically includes different types of interconnects that enable interconnection for data and/or signal transfer between two end points or devices. PCI and PCI Express (PCIe) are two such interconnect standard that can be utilized in some IHSes. PCI/PCIe is a bidirectional, point-to-point serial interconnect standard that is capable of high bandwidth data transfers up to 32 GB/s on an x16 connector. PCIe serves as a general purpose I/O interconnect for a wide variety of computing and communication platforms. The PCIe provides high speed, low pin count, and point-to-point transfers. A PCI Express link has two low-voltage, differential pairs of signals, a transmitting differential pair and a receiving differential pair. The bandwidth of a PCI Express link may be linearly scaled by adding differential pairs to form multiple lanes. The PCI Express currently supports from 1 to 32 lanes denoted as x1, x2, x4, x8, x16, or x32 lanes wherein each byte is transmitted with encoding across the lanes.
PCIe is based on point-to-point topology, with separate serial links connecting every device to the host with PCI Express port. The PCIe link supports full duplex communication between any two endpoints, with concurrent access across multiple endpoints. This configuration makes PCIe not interchangeable. The interconnection from the host, such as a CPU designated port, to a PCI Express slot is hardwired in the printed board circuit (PBC). A typical server allocates PCI lanes designed to a certain endpoint, and the PCI lanes cannot be reallocated. In a dense and high performance environment with multiple CPUs and high density of end points, the limit of PCI ports with certain bandwidth on the CPU to certain endpoints leads to a decrease in potential performance.